Wafer level diode package structure

ABSTRACT

A wafer level vertical diode package structure includes a first semiconductor layer, a second semiconductor layer, an insulative unit, a first conductive structure, and a second conductive structure. The second semiconductor layer is connected with one surface of the first semiconductor layer. The insulative unit is disposed around a lateral side of the first semiconductor layer and a lateral side of the second semiconductor layer. The first conductive structure is formed on a top surface of the first semiconductor layer and on one lateral side of the insulative layer. The second conductive structure is formed on a top surface of the second semiconductor layer and on another opposite lateral side of the insulative layer.

CROSS REFERENCE TO RELATED APPLICATION

This application is a continuation application of U.S. application Ser.No. 12/318,876, filed on 12 Jan. 2009 and entitled “WAFER LEVEL VERTICALDIODE PACKAGE STRUCTURE AND METHOD FOR MAKING THE SAME”, currentlypending.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a diode package structure, andparticularly relates to a wafer level vertical diode package structure.

2. Description of Related Art

Referring to FIG. 1, the prior art provides a diode package structurethat includes a P-type semiconductor layer P, an N-type semiconductorlayer N, a metal wire L and a package colloid C. The P-typesemiconductor layer P connects with the N-type semiconductor layer N.The N-type semiconductor layer N is electrically disposed on a PCB(Printed Circuit Board) D directly, and the P-type semiconductor layer Pis electrically connected to the PCB D via the metal wire L. Inaddition, the P-type semiconductor layer P, the N-type semiconductorlayer N and the metal wire L are enclosed by the package colloid C. Thediode package structure of the prior art can be used as a passiveelement.

However, the diode package structure has the following drawbacks:

1. The wire-bonding process using metal wire L and the package processusing the package colloid C are necessary in the prior art. Hence, thematerial cost and the manufacturing cost are increased.

2. The P-type semiconductor layer P is electrically connected to the PCBD via the metal wire L, so that the electrical path is long. Hence, theelectric conductivity of the prior art is bad.

SUMMARY OF THE INVENTION

One particular aspect of the present invention is to provide a waferlevel vertical diode package structure and a method for making the same.The present invention uses at least one insulative layer and at leasttwo conductive structures to package a P-type semiconductor layer and anN-type semiconductor layer that connects to the P-type semiconductorlayer. In addition, the two conductive structures is vertically andelectrically disposed on a PCB directly, so that the wafer levelvertical diode package structure is vertically and electrically disposedon the PCB.

In order to achieve the above-mentioned aspects, the present inventionprovides a wafer level vertical diode package structure, including: afirst semiconductor layer, a second semiconductor layer, an insulativelayer, a first conductive structure, and a second conductive structure.The second semiconductor layer is connected with one surface of thefirst semiconductor layer. The insulative layer is selectively disposedaround one part of a lateral side of the first semiconductor layer,around the lateral side of the first semiconductor layer, or around thelateral side of the first semiconductor layer and one part of a lateralside of the second semiconductor layer. The first conductive structureis formed on a top surface of the first semiconductor layer and on a topsurface of the insulative layer. The second conductive structure isformed on a top surface of the second semiconductor layer.

In order to achieve the above-mentioned aspects, the present inventionprovides a wafer level vertical diode package structure, including: afirst semiconductor layer, a second semiconductor layer, an insulativeunit, a first conductive structure, and a second conductive structure.The second semiconductor layer is connected with one surface of thefirst semiconductor layer. The insulative unit is disposed around alateral side of the first semiconductor layer and a lateral side of thesecond semiconductor layer. The first conductive structure is formed ona top surface of the first semiconductor layer and on one lateral sideof the insulative layer. The second conductive structure is formed on atop surface of the second semiconductor layer and on another oppositelateral side of the insulative layer.

In order to achieve the above-mentioned aspects, the present inventionprovides a method for making a wafer level vertical diode packagestructure, including: providing a diode wafer that has a firstsemiconductor unit and a second semiconductor unit connected with abottom side of the first semiconductor unit; forming a plurality ofgrooves interlaced with each other and passing through the firstsemiconductor unit and one part of the second semiconductor unit;forming an insulative unit in the grooves; forming a first conductiveunit on a top surface of the first semiconductor unit and on a topsurface of the insulative unit; overturning the diode wafer in order tomake the second semiconductor unit face up; forming a second conductiveunit on a top surface of the second semiconductor unit; and cutting thesecond conductive unit, the second semiconductor unit, the insulativeunit and the first conductive unit in sequence along the grooves inorder to form a plurality of second conductive structures, a pluralityof insulative layers and a plurality of first conductive structures.

In order to achieve the above-mentioned aspects, the present inventionprovides a method for making a wafer level vertical diode packagestructure, including: providing a diode wafer that has a firstsemiconductor unit and a second semiconductor unit connected with abottom side of the first semiconductor unit; forming a plurality offirst grooves interlaced with each other and passing through the firstsemiconductor unit and one part of the second semiconductor unit;forming a first insulative unit in the first grooves; forming a firstconductive unit on a top surface of the first semiconductor unit and ona top surface of the first insulative unit; overturning the diode waferin order to make the second semiconductor unit face up; forming aplurality of second grooves passing through one part of the secondsemiconductor unit in order to expose the first insulative unit; forminga second insulative unit in the second grooves in order to connect thefirst insulative unit with the second insulative unit, the firstsemiconductor unit being divided into a plurality of first semiconductorlayers and the second semiconductor unit being divided into a pluralityof second semiconductor layers respectively connected with the firstsemiconductor layers; forming a second conductive unit on a top surfaceof the second semiconductor unit and a top surface of the secondinsulative unit; and cutting the second conductive unit, the secondinsulative unit, the first insulative unit and the first conductive unitin sequence along the first grooves or the second grooves in order toform a plurality of second conductive structures, a plurality of secondinsulative layers, a plurality of first insulative layers and aplurality of first conductive structures.

Therefore, the present invention has the following advantages:

1. The wire-bonding process using metal wire and the package processusing the package colloid are unnecessary in the present invention.Hence, the material cost and the manufacturing cost are decreased in thepresent invention.

2. The wafer level vertical diode package structure is electricallydisposed on the PCB via the two conductive structures directly, so thatthe electrical path is short. Hence, the electric conductivity of thepresent invention is good.

3. The wafer level vertical diode package structure is cut from a diodewafer directly, so that the wafer level vertical diode package structuredoes not need to be grinded.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed. Otheradvantages and features of the invention will be apparent from thefollowing description, drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The various objects and advantages of the present invention will be morereadily understood from the following detailed description when read inconjunction with the appended drawings, in which:

FIG. 1 is a cross-sectional view of a diode package structure of theprior art;

FIG. 2 is a flowchart of a method for making a wafer level verticaldiode package structure according to the first embodiment of the presentinvention;

FIGS. 2A1 to 2I1 are cross-sectional views of a wafer level verticaldiode package structure according to the first embodiment of the presentinvention, at different stages of the packaging processes, respectively;

FIG. 2I2 is a perspective view of a wafer level vertical diode packagestructure according to the first embodiment of the present invention;

FIG. 2J is a cross-sectional view of a wafer level vertical diodepackage structure electrically disposed on a PCB via solder ballsaccording to the first embodiment of the present invention;

FIG. 2K is a cross-sectional view of a wafer level vertical diodepackage structure electrically disposed on a PCB via solder glueaccording to the first embodiment of the present invention;

FIG. 3A is a cross-sectional view of a wafer level vertical diodepackage structure according to the second embodiment of the presentinvention;

FIG. 3B is a cross-sectional view of a wafer level vertical diodepackage structure according to the third embodiment of the presentinvention;

FIG. 3C is a cross-sectional view of a wafer level vertical diodepackage structure according to the fourth embodiment of the presentinvention;

FIG. 4 is a flowchart of a method for making a wafer level verticaldiode package structure according to the fifth embodiment of the presentinvention;

FIGS. 4A to 4I1 are cross-sectional views of a wafer level verticaldiode package structure according to the fifth embodiment of the presentinvention, at different stages of the packaging processes, respectively;

FIG. 4I2 is a perspective view of a wafer level vertical diode packagestructure according to the fifth embodiment of the present invention;

FIG. 4J is a cross-sectional view of a wafer level vertical diodepackage structure electrically disposed on a PCB via solder ballsaccording to the fifth embodiment of the present invention;

FIG. 4K is a cross-sectional view of a wafer level vertical diodepackage structure electrically disposed on a PCB via solder glueaccording to the fifth embodiment of the present invention; and

FIG. 5 is a cross-sectional view of a wafer level vertical diode packagestructure according to the sixth embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIGS. 2, 2A1-2I1 and 2I2, the first embodiment of thepresent invention provides a method for making a wafer level verticaldiode package structure. The method includes the following steps:

The step S100 is: referring to FIGS. 2, 2A1 and 2A2 (FIG. 2A1 is apartial cross-sectional view of FIG. 2A2), providing a diode wafer Wathat has a first semiconductor unit Pa and a second semiconductor unitNa connected with a bottom side of the first semiconductor unit Pa. Inaddition, the first semiconductor unit Pa can be a P-type semiconductorlayer and the second semiconductor unit Na can be an N-typesemiconductor layer; Alternatively, the first semiconductor unit Pa canbe an N-type semiconductor layer and the second semiconductor unit Nacan be a P-type semiconductor layer, according to differentrequirements.

The step S102 is: referring to FIGS. 2, 2B1 and 2B2 (FIG. 2B2 is apartial top view of FIG. 2B1), forming a plurality of grooves Gainterlaced with each other and passing through the first semiconductorunit Pa and one part of the second semiconductor unit Na.

The step S104 is: referring to FIGS. 2 and 2C, forming an insulativeunit Sa in the grooves Ga. For example, a solder mask layer is formed onthe first semiconductor unit Pa and in the grooves Ga firstly, and thena formed solder mask layer is filled in the grooves Ga only by exposing,developing and etching in sequence. The formed solder mask layer is theinsulative unit Sa formed in the grooves Ga.

The step S106 is: referring to FIGS. 2 and 2D, forming a first UBM(under bump metallization) layer C11 a on a top surface of the firstsemiconductor unit Pa and on a top surface of the insulative unit Sa.For example, the first UBM layer C11 a is formed on the top surface ofthe first semiconductor unit Pa and on the top surface of the insulativeunit Sa by non-electroplating, physical depositing, chemical depositing,sputtering or evaporating.

The step S108 is: referring to FIGS. 2 and 2E, forming a firstconductive layer C12 a on the first UBM layer C11 a. For example, thefirst conductive layer C12 a is formed on the first UBM layer C11 a byelectroplating or non-electroplating.

The step S110 is: referring to FIGS. 2 and 2F, forming a secondconductive layer C13 a on the first conductive layer C12 a. For example,the second conductive layer C13 a is formed on the first conductivelayer C12 a by electroplating or non-electroplating.

Hence, the step from S106 to S110 is: forming a first conductive unit C1a on a top surface of the first semiconductor unit Pa and on a topsurface of the insulative unit Sa. The first conductive unit C1 a has afirst UBM layer C11 a formed on the top surface of the firstsemiconductor unit Pa and on the top surface of the insulative unit Sa,a first conductive layer C12 a formed on the first UBM layer C11 a, anda second conductive layer C13 a formed on the first conductive layer C12a.

The step S112 is: referring to FIGS. 2 and 2G, overturning the diodewafer Wa in order to make the second semiconductor unit Na face up.

The step S114 is: referring to FIGS. 2 and 2H, the same to S106, forminga second UBM layer C21 a on a top surface of the second semiconductorunit Na.

The step S116 is: referring to FIGS. 2 and 2H, the same to S108, forminga first conductive layer C22 a on the second UBM layer C21 a.

The step S118 is: referring to FIGS. 2 and 2H, the same to S110, forminga second conductive layer C23 a on the first conductive layer C22 a.

In other words, the step from S114 to S118 is: forming a secondconductive unit C2 a on the top surface of the second semiconductor unitNa. In addition, the second conductive unit C2 a has a second UBM layerC21 a formed on the top surface of the second semiconductor unit Na, afirst conductive layer C22 a formed on the second UBM layer C21 a, and asecond conductive layer C23 a formed on the first conductive layer C22a.

The step S120 is: referring to FIGS. 2, 2H and 2I1-2I2 (FIG. 2I1 is across-sectional view of FIG. 2I2), cutting the second conductive unit C2a, the second semiconductor unit Na, the insulative unit Sa and thefirst conductive unit C1 a in sequence along the grooves Ga (along X-Xlines of FIG. 2H) in order to form a plurality of second conductivestructures C2 a′, a plurality of insulative layers Sa′ and a pluralityof first conductive structures C1 a′.

Hence, referring to FIGS. 2I1 and 2I2, in the step S120, the firstsemiconductor unit Pa is cut into a plurality of first semiconductorlayers Pa′, and the second semiconductor unit Na is cut into a pluralityof second semiconductor layers Na′ respectively connected with the firstsemiconductor layers Pa′. In addition, each first conductive structureC1 a′ has a first UBM layer C11 a′ formed on the top surface of thefirst semiconductor layer Pa′ and on the top surface of the insulativelayer Sa′, a first conductive layer C12 a′ formed on the first UBM layerC11 a′, and a second conductive layer C13 a′ formed on the firstconductive layer C12 a′. Each second conductive structure C2 a′ has asecond UBM layer C21 a′ formed on the top surface of the secondsemiconductor layer Na′, a first conductive layer C22 a′ formed on thesecond UBM layer C21 a′, and a second conductive layer C23 a′ formed onthe first conductive layer C22 a′.

Therefore, referring to FIGS. 2I1 and 2I2, the first embodiment of thepresent invention provides a wafer level vertical diode packagestructure, including: a first semiconductor layer Pa′, a secondsemiconductor layer Na′, an insulative layer Sa′, a first conductivestructure C1 a′ and a second conductive structure C2 a′.

Moreover, the second semiconductor layer Na′ is connected with onesurface of the first semiconductor layer Pa′. In addition, the firstsemiconductor layer Pa′ can be a P-type semiconductor layer (such asP-type silicon) and the second semiconductor layer Na′ can be an N-typesemiconductor layer (such as N-type silicon); Alternatively, the firstsemiconductor layer Pa′ can be an N-type semiconductor layer and thesecond semiconductor layer Na′ can be a P-type semiconductor layer,according to different requirements. Furthermore, the insulative layerSa′ is disposed around a lateral side of the first semiconductor layerPa′ and one part of a lateral side of the second semiconductor layerNa′.

In addition, the first conductive structure C1 a′ formed on a topsurface of the first semiconductor layer Pa′ and on a top surface of theinsulative layer Sa′. The first conductive structure C1 a′ has a firstUBM layer C11 a′ formed on the top surface of the first semiconductorlayer Pa′ and on the top surface of the insulative layer Sa′, a firstconductive layer C12 a′ formed on the first UBM layer C11 a′, and asecond conductive layer C13 a′ formed on the first conductive layer C12a′. Moreover, the second conductive structure C2 a′ formed on a topsurface of the second semiconductor layer Na′. The second conductivestructure C2 a′ has a second UBM layer C21 a′ formed on the top surfaceof the second semiconductor layer Na′, a first conductive layer C22 a′formed on the second UBM layer C21 a′, and a second conductive layer C23a′ formed on the first conductive layer C22 a′.

Hence, in each wafer level vertical diode package structure, the firstsemiconductor layer Pa′ is enclosed by the insulative layer Sa′, thefirst conductive layer C1 a′ and the second semiconductor layer Na′.

Referring to FIG. 2J, the first conductive structure C1 a′ and thesecond conductive structure C2 a′ are vertically and electricallydisposed on a PCB (Printed Circuit Board) P by at least two solder ballsB. In other words, the first conductive structure C1 a′ and the secondconductive structure C2 a′ are vertically and electrically disposed onthe PCB P, so that the wafer level vertical diode package structure isvertically and electrically disposed on the PCB P.

Referring to FIG. 2K, the first conductive structure C1 a′ and thesecond conductive structure C2 a′ are vertically and electricallydisposed on a PCB (Printed Circuit Board) P by at least two layers ofsolder glue B′. In other words, the first conductive structure C1 a′ andthe second conductive structure C2 a′ are vertically and electricallydisposed on the PCB P, so that the wafer level vertical diode packagestructure is vertically and electrically disposed on the PCB P.

Referring to FIG. 3A, the difference between the second embodiment andthe first embodiment (as shown in FIG. 2I1) is that: in the secondembodiment, a first semiconductor layer Pb′ has at least two conductivepads Ab insulated from each other, and a first conductive structure C1b′ has two conductive structures Xb respectively and electricallyconnected to the two conductive pads Ab and an insulative structure Ybdisposed between the two conductive structures Xb. Hence, the secondembodiment of the present invention can be applied to a passive elementwith many contact points.

Referring to FIG. 3B, the difference between the third embodiment andthe first embodiment (as shown in FIG. 2I1) is that: in the thirdembodiment, an insulative layer Sc′ is disposed around one part of alateral side of a first semiconductor layer Pc′.

Referring to FIG. 3C, the difference between the fourth embodiment andthe first embodiment (as shown in FIG. 2I1) is that: in the fourthembodiment, an insulative layer Sd′ is disposed around a lateral side ofthe first semiconductor layer Pd′.

In other words, in the first, the third and the fourth embodiments, theinsulative layer (Sa′, Sc′, Sd′) is selectively disposed around thelateral side of the first semiconductor layer Pa′ and one part of thelateral side of the second semiconductor layer Na′ (such as the firstembodiment), around one part of the lateral side of the firstsemiconductor layer Pc′ (such as the third embodiment), or around thelateral side of the first semiconductor layer Pd′ (such as the fourthembodiment).

Referring to FIGS. 4, 4A-4I1 and 4I2, the fifth embodiment of thepresent invention provides a method for making a wafer level verticaldiode package structure. The method includes the following steps:

The step S200 is: referring to FIGS. 4 and 4A, providing a diode waferWe that has a first semiconductor unit Pe and a second semiconductorunit Ne connected with a bottom side of the first semiconductor unit Pe.In addition, the first semiconductor unit Pe can be a P-typesemiconductor layer and the second semiconductor unit Ne can be anN-type semiconductor layer; Alternatively, the first semiconductor unitPe can be an N-type semiconductor layer and the second semiconductorunit Ne can be a P-type semiconductor layer, according to differentrequirements.

The step S202 is: referring to FIGS. 4 and 4B, forming a plurality offirst grooves G1 e interlaced with each other and passing through thefirst semiconductor unit Pe and one part of the second semiconductorunit Ne.

The step S204 is: referring to FIGS. 4 and 4C, forming a firstinsulative unit S1 e in the first grooves G1 e. For example, a soldermask layer is formed on the first semiconductor unit Pe and in the firstgrooves G1 e firstly, and then a formed solder mask layer is filled inthe first grooves G1 e only by exposing, developing and etching insequence. The formed solder mask layer is the first insulative unit S1 eformed in the first grooves G1 e.

The step S206 is: referring to FIGS. 4 and 4D, forming a first UBM(under bump metallization) layer C11 e on a top surface of the firstsemiconductor unit Pe and on a top surface of the first insulative unitS1 e. For example, the first UBM layer C11 e is formed on the topsurface of the first semiconductor unit Pe and on the top surface of thefirst insulative unit S1 e by non-electroplating, physical depositing,chemical depositing, sputtering or evaporating.

The step S208 is: referring to FIGS. 4 and 4D, forming a firstconductive layer C12 e on the first UBM layer C11 e. For example, thefirst conductive layer C12 e is formed on the first UBM layer C11 e byelectroplating or non-electroplating.

The step S210 is: referring to FIGS. 4 and 4D, forming a secondconductive layer C13 e on the first conductive layer C12 e. For example,the second conductive layer C13 e is formed on the first conductivelayer C12 e by electroplating or non-electroplating.

Hence, the step from S206 to S210 is: forming a first conductive unit C1e on a top surface of the first semiconductor unit Pe and on a topsurface of the first insulative unit S1 e. The first conductive unit Clehas a first UBM layer C11 e formed on the top surface of the firstsemiconductor unit Pe and on the top surface of the first insulativeunit S1 e, a first conductive layer C12 e formed on the first UBM layerC11 e, and a second conductive layer C13 e formed on the firstconductive layer C12 e.

The step S212 is: referring to FIGS. 4 and 4E, overturning the diodewafer We in order to make the second semiconductor unit Ne face up.

The step S214 is: referring to FIGS. 4 and 4F, forming a plurality ofsecond grooves G2 e passing through one part of the second semiconductorunit Ne in order to expose the first insulative unit S1 e. For example,the method for forming the second grooves G2 e is the same as the methodfor forming the first grooves G1 e in the step S202.

The step S216 is: referring to FIGS. 4 and 4G, forming a secondinsulative unit S2 e in the second grooves G2 e in order to connect thefirst insulative unit S1 e with the second insulative unit S2 e, thefirst semiconductor unit Pe being divided into a plurality of firstsemiconductor layers Pe′ and the second semiconductor unit Ne beingdivided into a plurality of second semiconductor layers Ne′ respectivelyconnected with the first semiconductor layers Pe′. In addition, eachfirst semiconductor layer Pe′ and each second semiconductor layer Ne′are combined to form a diode. For example, the method for forming thesecond insulative unit S2 e is the same as the method for forming thefirst insulative unit S1 e in the step S204.

The step S218 is: referring to FIGS. 4 and 4H, forming a second UBM(under bump metallization) layer C21 e on a top surface of the secondsemiconductor unit Ne (or on a top surface of the second semiconductorlayer Ne′) and on a top surface of the second insulative unit S2 e. Forexample, the second UBM layer C21 e is formed on the top surface of thesecond semiconductor unit Ne (or on the top surface of the secondsemiconductor layer Ne′) and on the top surface of the second insulativeunit S2 e by non-electroplating, physical depositing, chemicaldepositing, sputtering or evaporating.

The step S220 is: referring to FIGS. 4 and 4H, forming a firstconductive layer C22 e on the second UBM layer C21 e. For example, thefirst conductive layer C22 e is formed on the second UBM layer C21 e byelectroplating or non-electroplating.

The step S222 is: referring to FIGS. 4 and 4H, forming a secondconductive layer C23 e on the first conductive layer C22 e. For example,the second conductive layer C23 e is formed on the first conductivelayer C22 e by electroplating or non-electroplating.

Hence, the step from S218 to S222 is: forming a second conductive unitC2 e on the top surface of the second semiconductor unit Ne (or on thetop surface of the second semiconductor layer Ne′) and the top surfaceof the second insulative unit S2 e.

The second conductive unit C2 e has a second UBM layer C21 e formed onthe top surface of the second semiconductor unit Ne (or on the topsurface of the second semiconductor layer Ne′) and the top surface ofthe second insulative unit S2 e, a first conductive layer C22 e formedon the second UBM layer C21 e, and a second conductive layer C23 eformed on the first conductive layer C22 e.

The step S224 is: referring to FIGS. 4, 4H and 4I1-4I2 (FIG. 4I1 is across-sectional view of FIG. 4I2), cutting the second conductive unit C2e, the second insulative unit S2 e, the first insulative unit S1 e andthe first conductive unit C1 e in sequence along the first grooves G1 eor the second grooves G2 e (along Y-Y lines of FIG. 4H) in order to forma plurality of second conductive structures C2 e′, a plurality of secondinsulative layers S2 e′, a plurality of first insulative layers S1 e′and a plurality of first conductive structures C1 e′.

Hence, referring to FIGS. 4I1 and 4I2, each first conductive structureC1 e′ has a first UBM layer C11 e′ formed on the top surface of thefirst semiconductor layer Pe′ and on the top surface of the firstinsulative unit S1 e′, a first conductive layer C12 e′ formed on thefirst UBM layer C11 e′, and a second conductive layer C13 e′ formed onthe first conductive layer C12 e′. Each second conductive structure C2e′ has a second UBM layer C21 e′ formed on the top surface of the secondsemiconductor layer Ne′ and the top surface of the second insulativeunit S2 e′, a first conductive layer C22 e′ formed on the second UBMlayer C21 e′, and a second conductive layer C23 e′ formed on the firstconductive layer C22 e′.

Therefore, referring to FIGS. 4I1 and 4I2, the fifth embodiment of thepresent invention provides a wafer level vertical diode packagestructure, including: a first semiconductor layer Pe′, a secondsemiconductor layer Ne′, an insulative layer Se′, a first conductivestructure C1 e′ and a second conductive structure C2 e′.

Moreover, the second semiconductor layer Ne′ is connected with onesurface of the first semiconductor layer Pe′. In addition, the firstsemiconductor layer Pe′ can be a P-type semiconductor layer (such asP-type silicon) and the second semiconductor layer Ne′ can be an N-typesemiconductor layer (such as N-type silicon); Alternatively, the firstsemiconductor layer Pe′ can be an N-type semiconductor layer and thesecond semiconductor layer Ne′ can be a P-type semiconductor layer,according to different requirements.

Furthermore, the insulative unit Se′ is disposed around a lateral sideof the first semiconductor layer Pe′ and a lateral side of the secondsemiconductor layer Ne′. In addition, the insulative unit Se′ has afirst insulative layer S1 e′ disposed around a lateral side of the firstsemiconductor layer Pe′ and one part of a lateral side of the secondsemiconductor layer Ne′ and a second insulative layer S2 e′ disposedaround another part of the lateral side of the second semiconductorlayer Ne′.

In addition, the first conductive structure Cle′ formed on a top surfaceof the first semiconductor layer Pe′ and on a top surface of the firstinsulative layer S1 e′. The first conductive structure C1 e′ has a firstUBM layer C11 e′ formed on the top surface of the first semiconductorlayer Pe′ and on the top surface of the first insulative unit S1 e′, afirst conductive layer C12 e′ formed on the first UBM layer C11 e′, anda second conductive layer C13 e′ formed on the first conductive layerC12 e′.

Moreover, the second conductive structure C2 e′ formed on a top surfaceof the second semiconductor layer Ne′ and on a top surface of the secondinsulative layer S2 e′. The second conductive structure C2 e′ has asecond UBM layer C21 e′ formed on the top surface of the secondsemiconductor layer Ne′ and the top surface of the second insulativeunit S2 e′, a first conductive layer C22 e′ formed on the second UBMlayer C21 e′, and a second conductive layer C23 e′ formed on the firstconductive layer C22 e′.

Hence, in each wafer level vertical diode package structure, the firstsemiconductor layer Pe′ and the second semiconductor Ne′ are enclosed bythe insulative unit Se′ (the first insulative layer S1 e′ and the secondinsulative layer S2 e′), the first conductive structure C1 e′ and thesecond conductive structure C2 e′. In other words, the firstsemiconductor layer Pe′ and the second semiconductor layer Ne′ areenclosed by each first conductive unit C1 e′, each second conductiveunit C2 e′, each first insulative layer S1 e′ and each second insulativelayer S2 e′.

Referring to FIG. 4J, the first conductive structure C1 e′ and thesecond conductive structure C2 e′ are vertically and electricallydisposed on a PCB (Printed Circuit Board) P by at least two solder ballsB. In other words, the first conductive structure C1 e′ and the secondconductive structure C2 e′ are vertically and electrically disposed onthe PCB P, so that the wafer level vertical diode package structure isvertically and electrically disposed on the PCB P.

Referring to FIG. 4K, the first conductive structure C1 e′ and thesecond conductive structure C2 e′ are vertically and electricallydisposed on a PCB (Printed Circuit Board) P by at least two layers ofsolder glue B′. In other words, the first conductive structure C1 e′ andthe second conductive structure C2 e′ are vertically and electricallydisposed on the PCB P, so that the wafer level vertical diode packagestructure is vertically and electrically disposed on the PCB P.

Referring to FIG. 5, the difference between the sixth embodiment and thefifth embodiment (as shown in FIG. 4I1) is that: in the sixthembodiment, a first semiconductor layer Pf′ has at least two conductivepads Af insulated from each other, and a first conductive structure C1f′ has two conductive structures Xf respectively and electricallyconnected to the two conductive pads Af and an insulative structure Yfdisposed between the two conductive structures Xf. Hence, the sixthembodiment of the present invention can be applied to a passive elementwith many contact points.

In conclusion, the present invention uses at least one insulative layerand at least two conductive structures to package a P-type semiconductorlayer and an N-type semiconductor layer that connects to the P-typesemiconductor layer. In addition, the two conductive structures isvertically and electrically disposed on a PCB directly, so that thewafer level vertical diode package structure is vertically andelectrically disposed on the PCB.

Therefore, the present invention has the following advantages:

1. The wire-bonding process using metal wire and the package processusing the package colloid are unnecessary in the present invention.Hence, the material cost and the manufacturing cost are decreased in thepresent invention.

2. The wafer level vertical diode package structure is electricallydisposed on the PCB via the two conductive structures directly, so thatthe electrical path is short. Hence, the electric conductivity of thepresent invention is good.

3. The wafer level vertical diode package structure is cut from a diodewafer directly, so that the wafer level vertical diode package structuredoes not need to be grinded.

Although the present invention has been described with reference to thepreferred best molds thereof, it will be understood that the inventionis not limited to the details thereof. Various substitutions andmodifications have been suggested in the foregoing description, andothers will occur to those of ordinary skill in the art. Therefore, allsuch substitutions and modifications are intended to be embraced withinthe scope of the invention as defined in the appended claims.

1. A wafer level diode package structure, comprising: a firstsemiconductor layer having a peripheral cutting area formed on aperipheral surface thereof; a second semiconductor layer connected withthe first semiconductor layer, wherein the second semiconductor layerhas a peripheral cutting area formed on a peripheral surface thereof andsubstantially flush with the peripheral cutting area of the firstsemiconductor layer; an insulative unit disposed around and on the twoperipheral cutting areas of the first and the second semiconductorlayers, wherein the insulative unit has a peripheral cutting area formedon a peripheral surface thereof; a first conductive structure formed ona bottom surface of the first semiconductor layer and a bottom surfaceof the insulative unit, wherein the first conductive structure has aperipheral cutting area formed on a peripheral surface thereof andsubstantially flush with the peripheral cutting area of the insulativeunit; and a second conductive structure formed on a top surface of thesecond semiconductor layer and a top surface of the insulative unit,wherein the second conductive structure has a peripheral cutting areaformed on a peripheral surface thereof and substantially flush with theperipheral cutting area of the insulative unit.
 2. The wafer level diodepackage structure as claimed in claim 1, wherein the first semiconductorlayer is a P-type semiconductor layer, and the second semiconductorlayer is an N-type semiconductor layer.
 3. The wafer level diode packagestructure as claimed in claim 1, wherein the first semiconductor layeris an N-type semiconductor layer, and the second semiconductor layer isa P-type semiconductor layer.
 4. The wafer level diode package structureas claimed in claim 1, wherein the insulative unit is composed of afirst insulative layer and a second insulative layer, the firstinsulative layer is disposed around and on the peripheral cutting areaof the first semiconductor layer and one part of the peripheral cuttingarea of the second semiconductor layer, and the second insulative layeris disposed around and on the other part of the peripheral cutting areaof the second semiconductor layer.
 5. The wafer level diode packagestructure as claimed in claim 4, wherein the first insulative layer hasa top surface connected to a bottom surface of the second insulativelayer.
 6. The wafer level diode package structure as claimed in claim 1,wherein the first conductive structure has a first UBM layer formed onthe bottom surface of the first semiconductor layer and the bottomsurface of the insulative unit, a first conductive layer formed on thefirst UBM layer, and a second conductive layer formed on the firstconductive layer; wherein the second conductive structure has a secondUBM layer formed on the top surface of the second semiconductor layerand the top surface of the insulative unit, a first conductive layerformed on the second UBM layer, and a second conductive layer formed onthe first conductive layer.
 7. The wafer level diode package structureas claimed in claim 1, wherein the first conductive structure and thesecond conductive structure are vertically and electrically disposed ona PCB by at least two solder balls or at least two layers of solderglue.
 8. The wafer level diode package structure as claimed in claim 1,wherein the first semiconductor layer has at least two conductive padsinsulated from each other, and the first conductive structure has twoconductive structures respectively and electrically connected to the twoconductive pads and an insulative structure disposed between the twoconductive structures of the first conductive structure.